An on-chip design requires large process variation compensation, when VCO (voltage control oscillator) design is used. At frequencies up to several GHz, the ±10% variation in the values of capacitances can cause 300 MHz to 500 MHz variations in the frequency. These variation levels may require an integrated VCO frequency range to exceed many times the actual wanted frequency range because, for example, WCDMA (wideband code-division multiple access) band is only 120 MHz at a double operation frequency. Then the needed process-variation-calibration is now done with switchable capacitors at the VCO core. These switches need a digital control and some kind of information about the conditions inside the circuit after the processing.
The prior art solutions include getting some information about the conditions inside the circuit after performing processing of a pre-calibration circuit using a memory. This calibration is done each time the electronic device (e.g., mobile phone) is turned on. During the calibration, the calibration circuit is used to find the switch setting to achieve one predefined frequency at certain conditions (temperature, etc.). Using this information one can define other switch settings to find other frequency bands (if needed) with the design information; for example, one change up in a digital tuning setting can change the operation frequency by 50 MHz up. U.S. Pat. No. 6,639,474 B2, “Adjustable Oscillator”, by K. Asikainen et al. describes such an example of the pre-calibration circuit.
FIG. 1 shows one example among others of a block diagram for a phase locked loop (PLL) 11a with a digital tuning (pre-calibration) of a voltage controlled oscillator (VCO) 10 providing an output signal 20 with a stabilized frequency, according to the prior art. The control block 15 provides the pre-calibration discussed above by sending a control digital signal 22 to the VCO 10. The rest of the PLL 11a is conventional. Typically, it comprises an N-divider 12 (a frequency of the output signal 20 is divided by a pre-selected number N generating an output frequency signal 40), a phase detector 14 utilizing a reference frequency signal 48 and a low pass filter 16 in a feedback loop to the VCO 10. The phase detector 14 provides a dc voltage proportional to the frequency difference of an output frequency signal 40 (indicative of an VCO oscillator frequency fosc) and the reference frequency signal 48 (having a frequency fref) to the VCO 10 after filtering by the low pass filter 16.